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? semiconductor components industries, llc, 2011 october, 2011 ? rev. 2 1 publication order number: NCN5192/d NCN5192 hart modem description the NCN5192 is a single ? chip, cmos modem for use in highway addressable remote transducer (hart) field instruments and masters. the modem and a few external passive components provide all of the functions needed to satisfy ha rt physical layer requirements including modulation, demodulation, receive filtering, carrier detect, and transmit ? signal shaping. in addition, the NCN5192 also has an integrated dac for low-bom current loop slave transmitter implementation. the NCN5192 uses phase continuous frequency shift keying (fsk) at 1200 bits per second. to conserve power the receive circuits are disabled during transmit operations and vice versa. this provides the half ? duplex operation used in hart communications. features ? single ? chip, half ? duplex 1200 bits per second fsk modem ? bell 202 shift frequencies of 1200 hz and 2200 hz ? 3.0 v ? 5.5 v power supply ? transmit ? signal wave shaping ? receive band ? pass filter ? low power: optimal for intrinsically safe applications ? compatible with 3.3 v or 5 v microcontroller ? internal oscillator requires 460.8 khz, 920 khz or 1.8 mhz crystal or ceramic resonator ? spi communication ? integrated 16 bit sigma-delta dac ? meets hart physical layer requirements ? industrial temperature range of ? 40 c to +85 c ? available in 32 ? pin nqfp package ? these are pb ? free devices applications ? hart multiplexers ? hart modem interfaces ? 4 ? 20 ma loop powered transmitters http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 12 of this data sheet. ordering information marking diagram NCN5192 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package 32 1 qfn32 case 488am ncn 5192 awlyyww 1
NCN5192 http://onsemi.com 2 block diagram figure 1. block diagram NCN5192 demodulator logic rx hp filter rx comp carrier detect counter carrier comp sine shaper numeric controlled oscillator demodulator modulator crystal oscillator por bias NCN5192 kvde 201104 07 .1 rxaf vdd rxa rxafi rxd aref cdref txa cd txd rts reset cbias vdda vss vssa fsk _out fsk _in xin xout rxd _enh vpor jump cs dclk data dac dacref clk 2 clk 1 spi dac kick electrical specifications table 1. absolute maximum ratings (notes 1 and 2) symbol parameter min max units t a ambient temperature ? 40 +85 c t s storage temperature ? 55 +150 c v dd supply voltage ? 0.3 6.0 v v in , v out dc input, output ? 0.3 v dd + 0.3 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. cmos devices are damaged by high ? energy electrostatic discharge. devices must be stored in conductive foam or with all pins shunted. precautions should be taken to avoid application of voltages higher than the maximum rating. stresses above absolute maximum ra tings may result in damage to the device. 2. remove power before insertion or removal of this device.
NCN5192 http://onsemi.com 3 table 2. dc characteristics (v dd = 3.0 v to 5.5 v, v ss = 0 v, t a = ? 40 c to +85 c) symbol parameter v dd min typ max units v dd dc supply voltage 3.0 5.5 v v il input voltage, low 3.0 ? 5.5 v 0.3 * v dd v v ih input voltage, high 3.0 ? 5.5 v 0.7 * v dd v v ol output voltage, low (i ol = 0.67 ma) 3.0 ? 5.5 v 0.4 v v oh output voltage, high (i oh = ? 0.67 ma) 3.0 ? 5.5 v 2.4 v c in input capacitance of: analog inputs rxa digital inputs 2.9 25 3.5 pf pf pf i il /i ih input leakage current 500 na i oll output leakage current 10 a i dd total power supply current 175 350 600 a i dda static analog supply current 3.3 v 5.0 v 150 150 330 370 a a i ddq static digital current 0 30 a i ddd dynamic digital current 5.0 v 25 200 a a ref analog reference 3.3 v 5.0 v 1.2 1.235 2.5 2.6 v v cd ref (note 3) carrier detect reference (iaref ? 0.08 v) 3.3 v 5.0 v 1.15 2.42 v c bias comparator bias current (rbias = 500 k , iaref = 1.235 v) 2.5 a 3. the hart specification requires carrier detect (cd) to be active between 80 and 120 mvp ? p. setting cdref at aref ? 0.08 vdc will set the carrier detect to a nominal 100 mvp ? p. table 3. ac characteristics (v dd = 3.0 v to 5.5 v, v ss = 0 v, t a = ? 40 c to +85 c) (note 4) pin name description min typ max units rxa receive analog input leakage current frequency ? mark (logic 1) frequency ? space (logic 0) 1190 2180 1200 2200 150 1210 2220 na hz hz rxaf output of the high ? pass filter slew rate gain bandwidth (gbw) voltage range 150 0.15 0.025 v dd ? 0.15 v/ms khz v/ms rxafi carrier detect and receive filter input leakage current 500 na txa modulator output frequency ? mark (logic 1) frequency ? space (logic 0) amplitude (iaref 1.235 v) slew rate ? mark (logic 1) slew rate ? space (logic 0) loading (iaref = 1.235 v) 30 1196.9 2194.3 500 1860 3300 hz hz mv v/s v/s k rxd receive digital output rise/fall time 20 ns cd carrier detect output rise/fall time 20 ns 4. the modulator output frequencies are proportional to the input clock frequency (460.8 khz/920 khz/1.8 mhz).
NCN5192 http://onsemi.com 4 table 4. modem characteristics (v dd = 3.0 v to 5.5 v, v ss = 0 v, t a = ? 40 c to +85 c) parameter min typ max units demodulator jitter conditions 1. input frequencies at 1200 hz 10 hz, 2200 hz 20 hz 2. clock frequency of 460.8 khz 0.1% 3. input (rxa) asymmetry, 0 12 % of 1 bit table 5. ceramic resonator and crystal ? external clock specifications (v dd = 3.0 v to 5.5 v, v ss = 0 v, t a = ? 40 c to +85 c) parameter min typ max units resonator tolerance frequency 460.8 1.0 % khz crystal or resonator, 920 khz tolerance frequency 921.6 1.0 % khz crystal, 1.8 mhz tolerance frequency 1.843 1.0 % mhz external duty cycle amplitude 40 50 v oh ? v ol 60 % v table 6. dac characteristics (v dd = 3.0 v to 5.5 v, v ss = 0 v, t a = ? 40 c to +85 c) parameter min typ max units bandwidth 10 hz accuracy return ? to ? zero non return ? to ? zero 16 14 bit bit maximum output return ? to ? zero non return ? to ? zero avdd/2 avdd v v differential non ? linearity return ? to ? zero non return ? to ? zero 0.5 0.25 0.75 0.75 lsb lsb integral non ? linearity return ? to ? zero non return ? to ? zero 2.0 1.0 4.0 2.0 lsb lsb
NCN5192 http://onsemi.com 5 typical application figure 2. application diagram NCN5192 xout xin 1. 8 m hz cbias vss vssa c vdda hart & 4?20ma out hart in power 3.0 to 5.5 v txa cdref aref rxa rxaf rxafi vdda vdd rxd cd txd rts lm285 reset NCN5192 vpor kvde20110407.2 cs data clk kick dac vdda jump dacref clk2 clk1 rxd_enh
NCN5192 http://onsemi.com 6 NCN5192 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 figure 3. pin out NCN5192 in 32-pin nqfp (top view) sclk jump kick cs txa aref data vss cdref cbias vpor vdda rxa rxaf rxafi vssa reset txd rts vdd vss xin xout vssa clk2 vdd dac dacref rxd_enh cd rxd clk1 table 7. pin out summary 32 ? pin nqfp pin no. signal name type pin description 1 sclk input spi serial clock 2 data input spi serial data 3 jump input sigma ? delta modulator alarm condition value 4 kick input watchdog kick 5 cs input spi serial chip select 6 vss ground ground 7 txa output transmit data modulator output 8 aref input analog reference voltage 9 cdref input carrier detect reference voltage 10 cbias output comparator bias current 11 vpor input por measurement point 12 vssa ground analog ground 13 vdda power analog supply voltage 14 rxa input receive data m odulator input 15 rxaf output analog receive filter input 16 rxafi input analog receive comparator input 17 xout output crystal oscillator output 18 xin input crystal oscillator input 19 vssa ground analog ground 20 vss ground ground 21 vdd power digital supply voltage 22 rtsb input request to send 23 txd input input transmit data, transmit hart data stream from microcontroller 24 resetb open drain reset all digital logic when low 25 rxd output received demodulated hart data to microcontroller 26 cd output carrier detect output 27 rxd_enh output not[cd] or rxd 28 dacref input sigma ? delta modulator reference voltage 29 dac output sigma ? delta modulator output 30 vdd power digital supply voltage 31 clk1 output programmable clock output 1 32 clk2 output programmable clock output 2
NCN5192 http://onsemi.com 7 pin descriptions table 8. pin descriptions symbol pin name description aref analog reference voltage receiver reference voltage. normally 1.23 v is selected (in combination with vdda = 3.3 v). see table 2. cdref carrier detect reference voltage carrier detect reference voltage. the value should be 85 mv below aref to set the carrier detection to a nominal of 100 mv p ? p . resetb reset digital logic when at logic low (v ss ) this input holds all the digital logic in reset. during normal operation resetb should be at v dd . resetb should be held low for a minimum of 10 ns after v dd = 2.5 v as shown in figure no tag . rtsb request to send active ? low input selects the operation of the modulator. txa is enabled when this signal is low. this signal must be held high during power ? up. rxa analog receive input receive data demodulator input. accepts a hart 1200 / 2200 hz fsk modulated square wave serial data stream as input. rxafi analog receive comparator input positive input of the carrier detect comparator and the receiver filter comparator. txd digital transmit input input to the modulator accepts digital data in nrz form. when txd is low, the modu- lator output frequency is 2200 hz. when txd is high, the modulator output frequency is 1200 hz. xin oscillator input input to the internal oscillator must be connected to a parallel mode ceramic resonator when using the internal oscillator or grounded when using an external clock signal. xout oscillator output output from the internal oscillator must be connected to an external clock signal or to a parallel mode ceramic resonator when using the internal oscillator. clk1 programmable clock output output signal derived from oscillator output, frequency division set by internal register. clk2 programmable clock output output signal derived from oscillator output, frequency division set by internal register. as this signal is also used internally, the division should be set so that the output fre- quency is 460.8 khz cbias comparator bias current connection to the external bias resistor. r bias should be selected such that aref / r bias = 2.5 a 5 % cd carrier detect output output goes high when a valid input is recognized on rxa. if the received signal is greater than the threshold specified on cdref for four cycles of the rxa signal, the valid input is recognized. rxaf analog receive filter output the output of the three pole high pass receive data filter rxd digital receive output signal outputs the digital receive data. when the received signal (rxa) is 1200 hz, rxd outputs logic high. when the received signal (rxa) is 2200 hz, rxd outputs logic low. the hart receive data stream is only active if carrier detect (cd) is high. rxd_enh digital receive output, alternative not(ocd) or rxd txa analog transmit output transmit data modulator output. a trapezoidal shaped waveform with a frequency of 1200 hz or 2200 hz corresponding to a data value of 1 or 0 respectively applied to txd. txa is active when rtsb is low. txa equals 0.5 v when rtsb is high. sclk spi bus clock line serial communication clock line data spi bus data line serial communication data line. frames transmitted can either be 8 bit or 16 bit long. cs spi bus chip select serial communication chip select line. pulled high by microcontroller while a frame is transmitted. jump dac alarm value when a problem is detected, such as a clock failure or the watchdog going off, the dac will jump to the value set on this pin. dacref dac reference this is the high value of the output and can be connected to any voltage between aref and vdd. dac dac output output of a 16 bit sigma ? delta modulator kick watchdog kick periodically a pulse should be provided to reset the watchdog. this can be configured in internal registers for an internal 1.8khz signal, or to an external signal provided to this pin. vpor por input input to the por comparator. the voltage on this pin is compared with aref. an external resistor divider should divide the supply voltage to this pin. vdd digital power power for the digital modem circuitry vdda analog supply voltage power for the analog modem circuitry vss ground digital ground (and analog ground in the case of plcc package) vssa analog ground analog ground
NCN5192 http://onsemi.com 8 functional description the NCN5192 is a single-chip modem for use in highway addressable remote transducer (hart) field instruments and masters. the modem ic contains a transmit data modulator with signal shaper, carrier detect circuitry, an analog receiver, demodulator circuitry and an oscillator, as shown in the block diagram in figure 1. the modulator accepts digital data at its digital input txd and generates a trapezoidal shaped fsk modulated signal at the analog output txa. a digital ?1? or mark is represented with a frequency of 1200 hz. a digital ?0? or space is represented with a frequency of 2200 hz. the used bit rate is 1200 baud. the demodulator receives the fsk signal at its analog input, filters it with a band-pass filter and generates 2 digital signals: rxd: received data and cd: carrier detect. at the digital output rxd the original modulated signal is received. cd outputs the carrier detect signal. it goes logic high if the received signal is above 100 mvpp during 4 consecutive carrier periods. the oscillator provides the modem with a stable time base using either a simple external resonator or an external clock source. detailed description modulator the modulator accepts digital data in nrz form at the txd input and generates the fsk modulated signal at the txa output. pc20101117.1 sine shaper numeric controlled oscillator modulator txa txd rts fsk_out figure 4. modulator block diagram a logic ?1? or mark is represented by a frequency f m = 1200 hz. a logic ?0?or space is represented by a frequency f s = 2200 hz. t t bit = 833 s ?1? = mark 1.2 khz ?0? = space 2.2 khz kvde20110407.5 t bit = 454 s figure 5. modulation timing the numeric controlled oscillator (nco) works in a phase con tinuous mode preventing abrupt phase shifts when switching between mark and space frequency. the control signal ?request to send? (rtsb) enables the nco. when rtsb is logic low the modulator is active and NCN5192 is in transmit mode. when rtsb is logic high the modulator is disabled and NCN5192 is in receive mode. the digital outputs of the nco are shaped in the wave shaper block to a trapezoidal signal. this circuit controls the rising and falling edge to be inside the standard hart waveshape limits. figure 6 shows the transmit-signal forms captured at txa for mark and space frequency. the slew rates are sr m = 1860 v/s at the mark frequency and sr s = 3300 v/s at the space frequency. for aref = 1.235 v, txa will have a voltage swing from approximately 0.25 to 0.75 v dc . t (ms) 0 v txa 0.5 v 1 2 t (ms) v txa ?1? = mark; f m =1.2 khz ?0? = space; f s =2.2 khz kvde2011040 8 0 1 2 sr m = 1860 v/s 0.5 v sr s = 3300 v/s 0. 5 v 0.5 v figure 6. modulator shaped output signal for mark and space frequency at txa pin. demodulator the demodulator accepts a fsk signal at the rxa input and reconstructs the original modulated signal at the rxd output. figure 7 illustrates the demodulation process. t bit idle (mark) lsb msb idle (mark) t bit 8 data bits d0 start d1 d2 d3 d4 d5 d6 d7 stop par ?0? ?1? ?0? ?1? ?0? ?1? ?0? ?0? ?0? ?1? fsk_in rxd pc20101013.4 figure 7. modulation timing this hart bit stream follows a standard 11-bit uart frame with start, stop, 8 data ? and 1 parity bit. the communication speed is 1200 baud.
NCN5192 http://onsemi.com 9 receive filter and comparator the received fsk signal first is filtered using a band-pass filter build around the low noise receiver operational amplifier ?rx hp filter?. this filter blocks interferences outside the hart signal band. rx comp rx hp filter rxaf rxa rxafi aref demodulator hart in 1.235 v dc c 1 c 2 c 3 r 1 r 2 r 3 r 4 r 6 r 5 c 4 pc20101118 .2 15 m figure 8. demodulator receive filter and signal comparator the filter output is fed into the rx comparator. the threshold value equals the analog ground making the comparator to toggle on every zero crossing of the filtered fsk signal. the maximum demodulator jitter is 12 % of one bit given the input frequencies are within the hart specifications, a clock frequency of 460.8 khz ( 1.0 %) and zero input (rxa) asymmetry. carrier detect circuitry low hart input signal levels increases the risk for the generation of bit errors. therefore the minimum signal amplitude is set to 80 ? 120 mvpp. if the received signal is below this level the demodulator is disabled. this level detection is done in the carrier detector. the output of the demodulator is qualified with the carrier detect signal (cd), therefore, only rxa signals large enough to be detected (100 mv p-p typically) by the carrier detect circuit produce received serial data at rxd. figure 9. demodulator carrier and signal comparator rxd cd demodulator logic rx comp carrier detect counter carrier comp demodulator rxafi aref cdref 15 m filtered hart in 1.235 v dc v aref ?80mv kvde20110407.6 rxd_enh the carrier detect comparator shown in figure 9 generates logic low output if the rxafi voltage is below cdref. the comparator output is fed into a carrier detect block. the carrier detect block drives the carrier detect output pin cd high if rtsb is high and four consecutive pulses out of the comparator have arrived. cd stays high as long as rtsb is high and the next comparator pulse is received in less than 2.5 ms. once cd goes inactive, it takes four consecutive pulses out of the comparator to assert cd again. four consecutive pulses amount to 3.33 ms when the received signal is 1200 hz and to 1.82 ms when the received signal is 2200 hz. the dif ference between rxd and rxd_enh is evident when cd is low: rxd is then also low, while rxd_enh is then high. when cd is high, rxd and rxd_enh have the same output. miscellaneous analog circuitry voltage references the NCN5192 requires two voltage references, aref and cdref. aref sets the dc operating point of the internal operational amplifiers and is the reference for the rx comparator. if NCN5192 operates at v dd = 3.3 v the on semiconductor lm285d 1.235 v reference is recommended. the level at which cd (carrier detect) becomes active is determined by the dc voltage dif ference (cdref - aref). selecting a voltage difference of 80 mv will set the carrier detect to a nominal 100 mv p-p . bias current resistor the NCN5192 requires a bias current resistor r bias to be connected between cbias and v ss . the bias current controls the operating parameters of the internal operational amplifiers and comparators and should be set to 2.5 a. bias cbias opa aref 2. 5 a r bias pc20101118 .4 figure 10. bias circuit the value of the bias current resistor is determined by the reference voltage aref and the following formula: r bias aref 2.5 a the recommended bias current resistor is 500 k when aref is equal to 1.235 v. oscillator the clock signal used by NCN5192 can either be 460.8 khz, 921.6 khz or 1.8432 mhz. this can be provided by an external clock or a resonator or crystal connected to the internal oscillator.
NCN5192 http://onsemi.com 10 internal oscillator option the oscillator cell will function with a 460.8 khz, 921.6 khz or 1.8432 mhz crystal or ceramic resonator. a parallel resonant ceramic resonator can be connected between xin and xout. figure 11 illustrates the crystal option for clock generation using a 460.8 khz ( 1% tolerance) parallel resonant crystal and two tuning capacitors c x . the actual values of the capacitors may depend on the recommendations of the manufacturer of the resonator. typically, capacitors in the range of 100 pf to 470 pf are used. additionally, a resistor may be required between xout and the crystal terminal, depending on manufacturer recommendation. the NCN5192 ic uses clk2 as clock signal for the wave shaping and digital logic. this signal must be set 460.8 khz by activating the proper frequency division in the internal register (bit 1 and 2). the clk1 frequency division (bit 3 and 4) can be freely chosen. this programmable clock signal can be used to drive other ics such as a microcontroller and is not used internally in the NCN5192. xout xin c x c x 460.8 khz crystal oscillator pc20101118 . 5 figure 11. crystal oscillator external clock option it may be desirable to use an external clock as shown in figure 12 rather than the internal oscillator. in addition, the NCN5192 consumes less current when an external clock is used. minimum current consumption occurs with the clock connected to xout and xin connected to v ss . xout xin crystal oscillator pc20101118 .6 460.8 khz figure 12. oscillator with external clock reset the NCN5192 modem includes a power on reset block. an external resistor division of the supply voltage is required, and should be tied to pin vpor. this pin is attached to an internal comparator, and is compared to the aref voltage. when this comparator trips, the resetb pin will be pulled low and the ic will reset. after vpor returns to a valid level, the resetb pin will be held low for at least an additional 35 ms (may be longer depending on clock frequency). the resetb pin will also be pulled low when a microcontroller failure is detected. a watchdog will guard microcontroller communication by looking at the kick pin. when the microcontroller fails to provide a periodical pulse on this pin, the watchdog will pull down the resetb pin for 140 s. a rising edge should be provided to the ic at least every 53 ms. a 1.8 khz kick can also be provided internally if bit 5 of the internal register is set. if the watchdog kick is provided internally, the kick pin should be tied to vss. por vpor opa aref kvde 20110408 .1 vdd figure 13. power on reset block figure 14. 8 bit spi frame figure 15. 16 bit spi frame spi communication the spi bus on the NCN5192 is made up of three signals; data, sclk, and cs. the data is either 8 bits or 16 bits. in the case of 8 bits cs will go high for eight clock cycles of sclk and in the case of 16 bits cs will be high for 16 clock cycles of sclk, as can be seen on figures 14 and 15. cs should first go high at least one clock cycle before the other signals change. one clock cycle is 2.17 s at a master
NCN5192 http://onsemi.com 11 clock frequency of 460.8 khz. cs is clocked in at the falling edge of the clk1 clock to detect if the data is for the mode register or the dac. sclk can begin to clock in data serially to the chip on the falling edge of sclk. sclk should have a maximum frequency of 460.8 khz. the format of the data should be either 8 or 16 bits with the most significant bit first. data is shifted into the chip on the falling edge of sclk, and thus for correct operation data should change only on the rising edge of sclk. the first bit shifted in is the msb. if 14 bit dac communication is utilized, then two 0?s should precede the 14 bits, and 16 clock cycles on sclk should occur. once the data is shifted in, cs should go low no sooner than one clock cycle after the last rising edge of sclk. table 9. internal register description bit description 0 (lsb) 0 = dac in 14 ? bit mode 1 = dac in 16 ? bit mode 1 set the crystal divide so that clk2 is 460.8 khz bit 2 bit 1 0 0 crystal/2 0 1 crystal/4 1 0 crystal/1 1 1 crystal/4 2 3 set the crystal divide for clk1 bit 4 bit 3 0 0 crystal/2 0 1 crystal/4 1 0 crystal/1 1 1 crystal/4 4 5 0 = watchdog kick external (pin) 1 = watchdog kick internal (1.8 khz) 6 0 = rtz output format on dac 1 = non rtz output format on dac 7 (msb) 0 = rxd is low when carrier is off 1 = rxd is high when carrier is off setting this bit, changes the function of rxd to the function of rxd_enh internal register the NCN5192 has an 8 bit register to setup its internal operation. an 8 bit spi communication method is used to write to the mode register. if cs goes low after only 8 clock cycles of sclk the mode register will latch in the 8 bits which are shifted into the spi shift register. in table x an explanation of the usage of each bit is given. all bits are set to ?0? at reset. sigma delta dac the NCN5192 modem has an integrated sigma ? delta modulator for use in a current loop slave transmitter. through this dac, an analog value can be set and transmitted across the current loop. for more information on how to create a current loop slave transmitter, see application notes on the on semi website. the dac output will switch between 0 v and the voltage provided to dacref. to achieve maximum accuracy, the dacref voltage should be kept stable, so that power supply variations are not visible in the dac output. the sigma ? delta modulator output can be set through spi frames containing 14 or 16 significant bits. the length of the data frames can be set through bit 0 is the status register. the output of the dac can be set return to zero (rtz) or non ? rtz. this is important when the rise and fall time of the signal are not identical. this will cause a dc offset depending on the number of rising and falling edges. as the output bits of a sigma ? delta modulator are randomly arranged (ie. for the same setting we could get 01110000 or 01010100), the number of edges might vary over time for a non return to zero signal. setting the dac to ?return to zero? forces the output to have a rising and falling edge for each logic ?1? bit, so that no offset from pulse asymmetry can occur. however, this will decrease the range of the modulator to 50% of dacref, as the maximum duty cycle is 50% instead of 100% for nrz. when a clock failure is detected, using an internal oscillator, the dac output will jump to the level set by the jump pin, until the ic is reset or a rising flank is detected on kick. table 10. spi frame format description bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode register 8 mode register data dac ? 14 bits mode 16 0 0 dac output word dac ? 16 bits mode 16 dac output word
NCN5192 http://onsemi.com 12 ordering information the NCN5192 is available in a 32 ? pin no lead quad flat pack (nqfp). use the following part numbers when ordering. contact your local sales representative for more information: www.onsemi.com . table 11. ordering information part number package shipping configuration temperature range NCN5192mng 32 ? pin nqfp green/rohs compliant ____ tube/tray ? 40 c to +85 c (industrial) NCN5192mnrg 32 ? pin nqfp green/rohs compliant ____ tape & reel ? 40 c to +85 c (industrial)
NCN5192 http://onsemi.com 13 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCN5192/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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